This invention relates generally to digital electronic circuits and more particularly to error detection and correction in asynchronous digital electronic circuits.
The majority of operations within a digital electronic circuit are synchronous: i.e. the various gates, flip-flops, registers etc. within the circuit are synchronized by clock pulses generated by a mater clock. This synchronization minimizes problems caused by the inherent delay of signals as they flow through the circuit by ensuring that the appropriate input signals are present before a circuit element is activated.
Asynchronous operation occurs when various elements within a circuit are not synchronized to the same clock. As noted in Microcomputer Interfacing, Harold S. Stone Addison-Wesley Publishing Company, 1983., pp. 108, the only way to be sure that a system is free from clocking difficulties is to use a single master clock from which all other timing is derived. Therefore, asynchronous operation is inherently subject to clocking errors which must be detected and hopefully remedied to ensure the proper operation of the asynchronous circuitry.
The problem of asynchronous operation can be exemplified by the prior art asynchronous latching circuit illustrated in FIG. 1a. The circuit includes a leading edge triggered, D-type flip-flop 10 having a D input, a Q output and a C input coupled to a clock signal. The Q output of the flip-flop 10 is coupled to a D input of a latch 12. The latch 12 has an E input coupled to an enable signal and a Q output which is latched to the value of the D input when the enable signal goes high. The clock signal and the enable signal are completely asynchronous, i.e. there is no relationship between the frequency, timing or duration of the two signals. Due to this lack of synchronization a "race condition" error can occur at the Q output of the latch 12.
The race, in this particular example, is along the data line 14 coupling the Q output of flip-flop 10 to the D input of latch 12. In FIG. 1b the clock and enable signals are shown along with the OUT1 signal and the Q output of flip-flop 10 and the OUT2 signal at the Q output of the latch 12. As seen in this figure, there is no relationship between the regular pulses of the clock and the asynchronous enable signal. The OUT1 signal is briefly indeterminate at points 16 when the flip-flop 10 is triggered by the leading edge of a clock pulse. Likewise, the OUT2 signal is indeterminate at points 18 whenever the latch 12 is enabled by the leading edge of the enable signal or by the leading edge of the clock signal when the enable signal is already high.
A race problem occurs when the latch 12 is attempting to latch the value at its D input to its Q output at the same time that the OUT1 signal is indeterminate. This is illustrated at a time t.sub.1 in FIG. 1b where the leading edge of the clock has produced an indeterminate OUT1 signal at the same time that the trailing edge of the enable signal is trying to latch the latch 12. If the OUT1 signal out-races the latching delay of latch 12 the proper data is latched at the Q output of the latch 12. On the other hand, if the OUT1 signal loses the race potential garbage G may be latched at the Q output of latch 12. As used herein, "garbage" means that the output state of the latch is completely unknown in that it could be a logic 0, a logic 1, a metastable state in between the two, or some oscillatory or transitory state. Once created, the garbage G may persist until the latch 12 is enabled at a time t.sub.2 with the leading edge of an enable pulse.
While a race problem in a particular asynchronous latch circuit may be fairly rare it is still problematic in digital system where data integrity is taken for granted. Moreover, when a digital system includes a number of asynchronous latch circuits combined into a multi-bit register the cumulative race problems may be substantial leading to significant data errors. Since each latch circuit in a register has its own, slightly different propagation rate, old data, new data and/or garbage may be present at the various output bits of the register during race conditions. For example, the data in one latch circuit may win the race resulting in new data in a register bit, while the data in another, slightly slower latch circuit may lose the race resulting in old data or garbage in another register bit. Since registers typically include information used to direct the action of logic circuitry, these race condition generated errors should be avoided if at all possible.
In a specific example, a common asynchronous circuit is the Universal Asynchronous Receiver Transmitter (UART) which includes several registers each of which may include a number of asynchronous latch circuits. Typically, one of these UART registers includes an error register comprised of a number of asynchronous latch circuits which indicate certain transmission/reception errors by an appropriate pattern of bits and the luck transmission/reception errors by all low bits. If the error register is subject to race conditions old data, new data and/or garbage may be present in the various bits of the register which could result in inappropriate actions being taken by the system receiving data from or sending data to the UART. Since the race condition problem cannot be eliminated from asynchronous circuits, it is therefore imperative to detect such problems and to take appropriate corrective actions.